In Q4 2025, Intel Foundry posted revenue of $4.5 billion alongside an operating loss of $2.5 billion. CEO Lip-Bu Tan admitted that “the company invested too much, too fast, without sufficient demand,” and Intel’s SEC filing included risk language to the effect that the company has yet to secure meaningful external foundry customers at scale on any of its nodes.
Framing Intel Foundry’s difficulties as simply a matter of “trust deficit” misses the point. The foundry business is far more technical, far more structural, and far more dependent on the compounding effects of time and volume than that narrative suggests.
1. Why Is the Foundry Business So Hard? The Moat Built from Technical Accumulation
The core barrier to entry in the foundry business is not any single technology. It is the compounding effect of technical assets built up over decades. Tracing the full journey from chip design to volume production reveals a wall at every stage that latecomers struggle to climb. This section examines the key technologies that define the foundry industry.
The Design Entry Requirement: PDK and IP Ecosystem
Before a fabless company can manufacture chips at a given foundry, it needs a PDK, or Process Design Kit. A PDK packages a foundry’s process information into a form that design engineers can actually use. It includes the layouts of basic devices like transistors, SPICE models for simulating electrical behavior, thousands of design rules, and technology files that allow EDA tools to analyze designs against the physical characteristics of that specific process.
The most important concept here is MHC, or Model-to-Hardware Correlation. In plain terms, MHC asks: “Does the silicon behave the way the simulation predicted?” How accurately a PDK’s SPICE models reflect the actual behavior of fabricated silicon is one of the most critical measures of a foundry’s technical competence. What happens when MHC breaks down? A customer who invested tens of millions of dollars to tape out a chip discovers it doesn’t perform as expected. That customer never comes back.
TSMC’s PDK is as powerful as it is because over thirty-
plus years of producing chips for thousands of customers, the accumulated silicon data has continuously recalibrated and refined model accuracy. Where does Intel stand by comparison? Intel’s 18A PDK 1.0 was released in July 2024, and the company has reported more than 100 tapeouts, but by most industry assessments, it remains far from reaching the level of MHC validation that TSMC has achieved.
A PDK alone isn’t enough, either. In SoC design, complex functional blocks like CPU cores, PCIe interfaces, and DDR controllers are typically sourced as pre-verified IP. Those IP blocks must be silicon-proven on the specific process at the specific foundry. IP validated for TSMC cannot simply be ported to Intel 18A. Physical design must be redone, timing constraints must be re-established, and silicon validation must start from scratch. That process takes a minimum of 12 to 18 months.
TSMC’s Open Innovation Platform has thousands of silicon-proven IP blocks registered to it. The reason IP vendors build for TSMC first is simple: TSMC has the most customers, so the ROI is highest. Because Intel has fewer customers, it has less IP, and because it has less IP, fewer customers come. The cycle feeds on itself.
Manufacturing Capability: The Invisible Asset Called BKM
In semiconductor manufacturing, BKM stands for Best Known Methods. These are the best currently understood approaches to each of the hundreds to thousands of process steps in an advanced node. The optimal exposure conditions for lithography, the gas flow and pressure combinations for etching, the polish time and pressure for CMP — BKM is the optimized combination of every parameter. Critically, today’s BKM is not the final answer. When a better method is found, it gets updated.
BKM isn’t learned by reading papers in a lab. It comes from running actual wafers, accumulating process response data across a wide variety of design patterns, discovering unexpected defect modes, and finding solutions. The more wafers you run, the faster you find and resolve problems.
This is where the scale effect of foundries kicks in. TSMC simultaneously produces chips for hundreds of customers with vastly different designs, generating enormous wafer volumes. Through that process, solutions to diverse defect modes are codified as BKM, and every customer on the same process benefits. Intel Foundry, with almost no external customers, is accumulating BKM primarily through its own x86 processors. It lacks process data across the wide variety of design patterns found in mobile APs, AI accelerators, networking chips, and beyond.
Yield and Cost: The Core Equation of Foundry Economics
All of this technical accumulation converges on yield. The single most critical variable determining foundry economics is defect density, or D₀, which represents the number of critical defects per unit area of wafer.
At D₀ = 0.40 with a die area of 1 cm², yield is roughly 67%. Improve D₀ to 0.10 and yield jumps to around 90%. Translating that yield difference into dollars reveals the severity of the problem. The cost of a single leading-edge 2nm-class wafer is estimated at over $20,000. At 65% yield, 65 out of 100 dies per wafer are good. At 90%, 90 are. The per-die cost difference exceeds 38%.
Add fab utilization to the equation. A leading-edge fab costs billions of dollars per year to operate, and those fixed costs accrue whether or not wafers are running. At 50% utilization, fixed cost allocation per die nearly doubles compared to 80% utilization. Intel Foundry losing $2.5 billion per quarter is a structural consequence of low yield and low utilization compounding simultaneously.
Yield improvement follows a learning curve. Early on, systematic factors like equipment setup, process conditions, and process windows dominate defect behavior. Over time, the contest shifts to how quickly you can drive down random defect density. In that phase, the decisive variable is how many wafers, with how many diverse patterns, are run how frequently. More volume means defects are observed faster, root causes are isolated sooner, and BKM gets updated more rapidly. Yield matures faster within the same timeframe.
This is why large foundries can immediately ramp utilization at the start of a new node and simultaneously produce a diverse mix of customer designs, maximizing the speed of learning. A foundry with limited external volume has less learning data, slower yield maturation, and a structural disadvantage in per-wafer cost and delivery reliability. That cost and reliability gap makes it harder to win customers, perpetuating volume shortfall, which slows yield learning further. The cycle compounds.
PDK maturity, BKM depth, and yield learning speed are all functions of time and volume. Once the virtuous cycle starts spinning, the gap with latecomers widens exponentially. That is the substance of the moat TSMC has been building for more than thirty years.
2. Where Does Intel Foundry Stand Today?
Intel 18A: Production Has Started, But There Are Still No External Customers
Intel 18A is understood to have entered serious production ramp in the second half of 2025. Intel has positioned 18A as the process that first brings RibbonFET (GAA) and PowerVia (backside power delivery) to high-volume manufacturing simultaneously, and has emphasized that this combination represents the first instance of that approach reaching production scale. The Core Ultra Series 3 — the Panther Lake family — has been cited as the first product on the node, with Clearwater Forest, the server variant, also named on the roadmap. There have been reports of CEO Lip-Bu Tan offering positive assessments suggesting 18A progress has been ahead of expectations.
Yield has not been officially disclosed, and various estimates circulate in the press and industry. Some sources have floated numbers in the low-to-mid 60% range. On the PDK side, Intel announced the release of 18A PDK 1.0 in July 2024, and tapeouts are ongoing.
The fundamental issue, however, is who that technical progress is for. Everything known about 18A’s advancement is largely anchored to Intel’s own products. Intel’s SEC filings have repeatedly included risk language noting that external customer volume remains limited. In short: the process is running, but the external volume, trust, and scale that a foundry business actually requires have yet to be demonstrated.
The external-customer-facing variant, 18A-P, is in preparation. There are indications that the 18A-P PDK has been delivered to select customers for evaluation, and some observers expect customer qualification and production discussions to accelerate around 2026. Ultimately, the true test for Intel as a foundry is not the internal success of 18A itself, but whether external customers actually commit volume to 18A-P.
Compared to TSMC N2: Behind on Density, Cost, and Ecosystem
Intel 18A’s direct competitor is TSMC N2. The two processes compete in the same 2nm-class generation, but the axes on which each is perceived to be strong differ considerably.
Intel has made strong claims about performance and power efficiency. The company has presented data showing performance gains at equivalent voltage, or power savings at equivalent performance, under specific comparison conditions using ARM cores, pointing to PowerVia as the underlying technology. PowerVia separates the power network to the backside of the chip, freeing up frontside routing resources for signal and reducing IR drop. The logic is compelling on paper, promising to alleviate design bottlenecks. That said, process-to-process performance comparisons depend heavily on product configuration and design methodology, and for external customers, silicon reproducibility and production data will ultimately matter most.
On density, TSMC holds a clear lead. TSMC N2 achieves 313 million transistors per square millimeter versus Intel 18A’s 238 million. Higher density means smaller dies for the same chip, which means lower cost per die. PowerVia does reclaim some frontside area, so the “effective density” gap may be smaller than the raw numbers suggest, but the additional process steps required for backside power delivery likely push Intel’s wafer manufacturing cost higher.
Yield gaps are also expected to be meaningful. Exact figures aren’t available, but Intel has not publicly disclosed 18A yield numbers, while TSMC has a longstanding industry reputation for rapid yield ramp and volume-driven learning. More fundamentally, the real comparison isn’t the current yield percentage but the rate of maturation. As the yield economics discussed earlier make clear, a difference in ramp speed directly translates into differences in per-die cost and delivery reliability.
The ecosystem comparison is almost impossible to make on equal terms. TSMC’s OIP has thousands of silicon-proven IP entries. Intel 18A’s IP ecosystem is just beginning to be built. More fundamentally, Intel’s PowerVia is incompatible with existing front-side power delivery IP. Adapting to a backside power delivery process requires fundamentally redesigning the power routing architecture, which is not a simple port but something closer to a full IP redevelopment. TSMC, meanwhile, is running a dual-track strategy: FSPD on N2 and BSPD on A16 (targeting 2026 to 2027), giving customers a choice. Intel is single-track on BSPD.
Taken together, Intel’s positioning is clear. There is a competitive case in premium HPC and AI markets where performance matters most, but mobile and IoT markets driven by cost and density remain structurally out of reach for now. The addressable market is inherently narrow.
Looking at thecplayers side by side, the roles become distinct. TSMC remains the benchmark. Intel is targeting specific high-performance segments with PowerVia as its differentiator.
The Narrowing Window of Opportunity
The “multi-sourcing” strategies of fabless customers are creating a structural opportunity for Intel. Apple, Nvidia, AMD, and Qualcomm all want to reduce their risk from single-source dependence on TSMC. GlobalFoundries has already stepped off the leading-edge treadmill. Rapidus in Japan is targeting 2nm but has no production track record, with volume manufacturing expected no earlier than 2027.
But that window is narrowing andcTSMC isn’t standing still. Its N4 fab in Arizona is in operation, JASM in Kumamoto, Japan is running, and a fab is under construction in Dresden, Germany. The geopolitical premium Intel derives from domestic U.S. production is being diluted with each passing quarter.
That makes 2026 and 2027 a time problem for Intel. If Intel cannot demonstrate, within that window, the production reproducibility and ecosystem depth that external customers require, those customers will either stay with the proven TSMC or turn toward a resurgent Samsung.
3. Intel’s Survival Strategy: Customers, Challenges, and Scenarios
The Customer Pipeline Taking Shape
Apple: The Name That Could Change Everything
Since late 2025, the hottest story in the industry has been the possibility of Apple becoming an Intel Foundry customer. According to analyst Ming-Chi Kuo, Apple has already received Intel’s 18A-P process PDK 0.9.1GA and is running internal simulations, with results reportedly meeting expectations. When PDK 1.0 arrives in Q1 2026, formal qualification is expected to begin in earnest.
The target products are entry-level M-series processors for the MacBook Air and iPad Pro, at an estimated annual volume of 15 to 20 million units. Starting with the lowest-tier chips rather than the Pro or Max line is realistic. From Apple’s perspective, it minimizes risk while validating Intel’s production capability, with room to expand volume incrementally if the results hold up. KeyBanc Capital Markets analyst John Vinh has gone further, indicating that Apple is in discussions about manufacturing entry-level iPhone A-series processors on Intel’s 14A process around 2029.
Apple’s motivation for considering Intel Foundry is straightforward. In the Q1 2026 earnings call, Tim Cook directly acknowledged supply constraints and expressed difficulty predicting when supply-demand balance would be restored. One hundred percent dependence on TSMC weakens Apple’s negotiating leverage and exposes it to geopolitical risk in the Taiwan Strait. The deal is not confirmed. The first half of 2026 will be the go/no-go inflection point.
Nvidia: A Cautious Approach, but a Meaningful Signal
Nvidia’s relationship with Intel is more complicated. In September 2025, Nvidia announced a $5 billion investment in Intel (completed in December, representing approximately 4% stake), with the two companies agreeing to collaborate on developing SoCs integrating x86 CPUs and Nvidia GPUs.
On the foundry side, signals have been mixed. Reuters reported that Nvidia tested Intel’s 18A process but “stopped moving forward,” with the interpretation being that yield and performance fell short of expectations. Nvidia had already secured TSMC N2 capacity for its next-generation 2nm-class designs, so the motivation for switching to Intel 18A was limited.
In January 2026, however, DigiTimes reversed the narrative. The report indicated that Nvidia is exploring manufacturing the I/O die for its next-generation GPU architecture, codenamed Feynman (expected around 2028), on Intel’s 18A or 14A process. The structure keeps the core GPU compute die with TSMC while assigning roughly 25% of I/O die work and advanced packaging via EMIB to Intel. This allows Nvidia to keep the most performance-sensitive compute die with a proven partner while using the I/O die as a lower-risk proving ground for Intel. It is a textbook foundry diversification strategy.
Microsoft and AWS: Anchor Customers Already in Motion
Beyond Apple and Nvidia, customers are already moving. Microsoft plans to produce Maia 2, its AI accelerator for Azure data centers, on Intel 18A. AWS is working with Intel on custom Xeon processors and AI fabric interconnect chips. The reason these hyperscalers are choosing Intel has less to do with technical superiority than with strategic diversification. With AI infrastructure demand exploding and TSMC’s advanced process capacity chronically constrained, securing alternative production capability on domestic U.S. soil is a rational supply chain resilience decision.
Five Thresholds Intel Must Clear
First: The yield inflection point in the first half of 2026. Before anything else, 18A process yield must reach a level sufficient to accept external customers. Volume production of Panther Lake (PC) and Clearwater Forest (server) needs to serve as the living proof of 18A’s maturity. No external customer will sign up for a process that can’t reliably produce Intel’s own chips.
Second: 18A-P must ship on time. If 18A is optimized for Intel’s own CPUs, 18A-P is the real foundry process. The timeline for PDK 1.0 and production ramp must align with the schedules of external customers, including Apple. In foundry, schedule slippage equals customer attrition.
Third: The real contest is 14A. Intel 18A is not the ideal process for most external foundry customers. The decisive battle shifts to 14A, expected around 2027, which would be the first commercial application of High-NA EUV lithography. If Intel can establish a genuine technical advantage over TSMC at that node, it could be a game changer. Intel has already declared, however, that it will not invest without customer commitments. The “build it and they will come” approach is no longer on the table.
Fourth: EMIB packaging as a side door. Intriguingly, the fastest path for Intel to attract foundry customers may not be wafer processing at all, but advanced packaging. Intel’s EMIB and Foveros technologies are best-in-class, and TSMC’s CoWoS packaging has been chronically supply-constrained under the surge in AI demand. The Nvidia Feynman deal is itself centered on EMIB. Packaging revenue may arrive ahead of wafer processing revenue, and it could be the foot-in-the-door that establishes relationships with foundry customers.
Fifth: Converting geopolitical tailwinds into execution. Taiwan Strait risk, $7.86 billion in direct CHIPS Act grants plus a separate government equity stake of approximately 9.9%, and U.S. Department of Defense demand for domestic production — all of these work structurally in Intel’s favor. But as TSMC Arizona ramps and Samsung Taylor comes online, this premium shrinks over time. Government subsidies can bridge early cost gaps, but Intel must independently build its technical competitiveness. The window is the period before TSMC Arizona and Samsung Taylor reach full capacity.
Two Scenarios
Bull Case: The Flywheel Starts Turning
PDK timelines hold. Internal product production proves process maturity. Apple and Nvidia commit meaningful volume. External customer inflows accelerate yield learning. 14A arrives on schedule, capturing the first-mover advantage of High-NA EUV. Foundry operating losses begin to shrink. By the end of the decade, Intel captures a meaningful share of the global foundry market.
Bear Case: The Window Closes
Process schedules slip. Production maturity disappoints. Apple defers its decision or limits engagement to a small pilot. Nvidia ultimately stays with TSMC. TSMC Arizona ramps and erodes the domestic-production premium. External customer volume fails to materialize. Large-scale losses persist. Investment in 14A is scaled back. Strategic retreat from the foundry business returns to the table.
Conclusion
Intel Foundry’s contest has moved past the stage of “potential” and into the stage of “proof.”
If 18A demonstrated the direction of the technology through internal products, 18A-P is the first gate through which external customers must decide whether to commit their trust and their tapeouts. If that gate is cleared and volume begins to flow, learning accelerates, the ecosystem follows, and 14A becomes the card that turns the game.
If that timing is missed, customers stay with the proven TSMC, the remaining alternatives are divided with Samsung, and Intel’s foundry strategy will once again face pressure to contract. Which scenario unfolds depends, in the end, on what Intel can execute from the inside.
